`ifndef UDLY
`define UDLY 1
`endif
module fft_ctrl__1(
  __clock,
  __resetn
);
//parameter declare
//port declare
input __clock;
input __resetn;
//channel declare
//wire declare
//port wire declare
wire __clock;
wire __resetn;
//register declare
//register init and update
//cell instance
endmodule
